GitHub - SarthakDubey/VHDL-Calculator: Simple VHDL Implementation of a calculator in a FPGA EECS 355
GitHub - JeanJuba/vhdl-calculator: Calculator that reads values from memory stored using reverse polish notation. The 4 operations supported are addition, subtraction, multiplication and division.
![GitHub - sean-krail/vhdl-single-cycle-calculator: My single-cycle 8-bit calculator that I designed in VHDL for CPEG324: Computer Systems Design. I used GHDL and GTKWave to simulate my designs. GitHub - sean-krail/vhdl-single-cycle-calculator: My single-cycle 8-bit calculator that I designed in VHDL for CPEG324: Computer Systems Design. I used GHDL and GTKWave to simulate my designs.](https://raw.githubusercontent.com/Krail/vhdl-single-cycle-calculator/master/.meta/project.png)